1. Field of the Invention
The present invention relates to a phase-locked loop clock signal generator.
2. Description of the Related Art
A frequency multiplying circuit for outputting a clock signal having a frequency twice that of an input signal, a phase-locked loop circuit, having an oscillator, for detecting a phase difference between input and output signals and performing a feedback control operation such that the frequency of the oscillator is always set to be several times that of an input signal and the phases of the input and output signals from the oscillator are locked to each other, and the like are arranged in a semiconductor integrated circuit as needed.
FIG. 1 is a circuit diagram showing an arrangement of a conventional frequency multiplying circuit which is a kind of a clock signal generator. FIG. 2 is a timing chart of the frequency multiplying circuit. An input clock signal CLKIN is supplied to one input terminal of an exclusive OR circuit 121 and an delay circuit 124 constituted by an inverter 122 and a capacitor 123. A delay output signal SA from the delay circuit 124 is supplied to an inverter 125. An output signal SB from the inverter 125 is supplied to the other input terminal of the exclusive OR circuit 121. A multiplied clock signal CLKOUT is obtained from the exclusive OR circuit 121.
FIG. 3 is a truth table showing logic states of input and output signals of the exclusive OR circuit 121. When the clock signal CLKIN and the output signal SB from the inverter 125 are input to the exclusive OR circuit 121, as shown in the timing chart of FIG. 2, the clock signal CLKOUT having a frequency twice that of the input clock signal CLKIN can be obtained.
FIG. 4 is a block diagram schematically showing an arrangement of a conventional phase-locked-loop (to be referred to as a PLL hereinafter) digital frequency synthesizer which is a kind of a clock signal generator. The oscillation frequency of a VCO (Voltage-Controlled Oscillator) 131 is controlled in accordance with the output potential of a low-pass filter 132, and the VCO 131 oscillates at a frequency higher than a reference input frequency fREF (the frequency fREF is N times the reference input frequency). The frequency f0 (=NfREF) obtained from the VCO 131 is supplied to other circuits requiring this frequency and is 1/N-divided by a frequency divider 133 to be input to a phase detector (phase comparator) 134. In the phase detector 134, the phase and frequency of the 1/N-divided frequency fREF is compared with the reference input frequency, and the comparison result is fed back to the VCO 131 through the low-pass filter 132. With the above arrangement, a high-frequency signal having a phase difference according to the reference input frequency can be obtained.
FIG. 5 shows a circuit arrangement of the phase detector used in the frequency synthesizer in FIG. 4. As shown in FIG. 5, the well-known edge-triggered phase detector constituted by several NAND gates and several inverters is used. In FIG. 5, reference symbol R denotes the reference input frequency, and reference symbol V denotes a frequency 1/N-divided by the frequency divider 133.
In the frequency multiplying circuit in FIG. 1, the input clock signal CLKIN is delayed and the output clock signal CLKOUT is obtained by using a phase difference between two input signals from the exclusive OR circuit 121. However, the characteristics of the inverter and the capacitances of the capacitor for obtaining a predetermined delay amount depend on variations in manufacturing conditions, and the characteristics of the inverter also depend on a power source voltage used and an ambient temperature. For this reason, the delay amount is not uniformed. Therefore, an "H"-level period (TH in FIG. 2) and an "L"-level period (TL in FIG. 2) of the output clock signal CLKOUT are changed every time these conditions are changed. In the worst case, the output clock signal CLKOUT becomes a so-called glitch-like signal in which the "H"-level period and "L"-level period are almost eliminated. According to circumstances, the signal may be continuously set at "H" level or "L" level.
In the frequency synthesizer in FIG. 4, since the edge-triggered phase detector is used, when a waveform division portion is formed in the reference input frequency due to noise or the like, this portion is erroneously counted as a part of the frequency. In addition, when the phase detector itself is incorporated in a semiconductor circuit device, in order to improve accuracy of phase comparison, symmetry between the circuit patterns of R and V input sides of the circuit in FIG. 5 is required. For this reason, a pattern area required for a phase divider is increased, and a chip area is disadvantageously increased.
In the frequency synthesizer in FIG. 4, since a frequency division ratio in the frequency divider must be set to be an integer, the output frequency f0 is limited to an integer multiple of the frequency fREF, and the output frequency f0 cannot have a decimal part, e.g., N=99.4 or N=15.6. Therefore, when the frequency fREF must be multiplied by a multiplier having a decimal part, the multiplier is rounded off, and frequency division is performed using the rounded multiplier, e.g., N=99 or N=16. However, in this case, since the multiplier N includes an error in advance, the error causes a problem such as jitter.
As described above, in the conventional clock signal generator, an output clock signal is not stably obtained by an influence of variations in manufacturing conditions or an influence of variations in application conditions due to voltage dependency.
In the conventional clock signal generator, especially in a digital frequency synthesizer, since an erroneous operation is easily performed by noise of an input clock signal, a special care must be taken for a circuit pattern. Therefore, the following drawbacks are caused. That is, a chip area is increased, a manufacturing cost is increased, and an output clock signal having a frequency which is an arbitrary number of times the input frequency and has a decimal part cannot be obtained.